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Material Detail

Multi-Threaded Pipelining in a RISC Processor

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Material Type: Case Study
Date Added to MERLOT: March 24, 2003
Date Modified in MERLOT: May 03, 2007
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Author: Ian Donald MacIntyre and Bruno Richard Preiss  Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, Ontario, Canada
Submitter :  Lehmann


This paper presents a model for predicting the CPI of a multi-threaded pipelined processor. It also presents the results of trace-driven simulations of single- and multi-threaded processors. These data show that, for reasonable implementation technologies, and taking into account the chip area penalty, a multi-threaded processor... More

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Primary Audience: Graduate School, Professional
Mobile Compatibility: Not specified at this time
Language: English
Cost Involved: no Source Code Available: no
Accessiblity Information Available: no Copyright: yes
Creative Commons: unsure

About this material:

  • Editor Review avg:3 stars
  • User Rating3.5
  • Discussion (2 Comments)
  • Learning Exercises (none)
  • Personal Collections (none)
  • Accessibility Info (none)


Discussion for Multi-Threaded Pipelining in a RISC Processor

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Avatar for   Nagel
11 years ago

Nagel (Student)

20 minutes, good content. Good look at pipelining with a RISC processor.
Learned quite a bit. A bit too detailed for someone not knowing much about
Used in course

Avatar for Matt Smith
11 years ago

Matt Smith (Student)

I spent about 20 minutes reviewing the material. It is very detailed and is not
an easy read. The material is useful and informative and does submit the
material in the textbook.
Used in course

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