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Multi-Threaded Pipelining in a RISC Processor

        

Multi-Threaded Pipelining in a RISC Processor

Logo for Multi-Threaded Pipelining in a RISC Processor
This paper presents a model for predicting the CPI of a multi-threaded pipelined processor. It also presents the results of trace-driven simulations of single- and multi-threaded processors. These data show that, for reasonable implementation technologies, and taking into account the chip area penalty, a multi-threaded processor can achieve a lower CPI than a single-threaded processor.
Material Type: Case Study
Date Added to MERLOT: March 24, 2003
Date Modified in MERLOT: May 03, 2007
Author:
Submitter: Lehmann

Quality

  • Reviewed by members of Editorial board for inclusion in MERLOT.
    Editor Review (not reviewed)
  • User review 3.5 average rating
  • User Rating: 3.5 user rating
  • Discussion (2 Comments)
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About

Primary Audience: Graduate School, Professional
Mobile Compatibility: Not specified at this time
Language: English
Cost Involved: no
Source Code Available: no
Accessiblity Information Available: no
Creative Commons: unsure

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Avatar for   Nagel
12 years ago

Nagel (Student)

20 minutes, good content. Good look at pipelining with a RISC processor.
Learned quite a bit. A bit too detailed for someone not knowing much about
processors.
Used in course

Avatar for Matt Smith
12 years ago

Matt Smith (Student)

I spent about 20 minutes reviewing the material. It is very detailed and is not
an easy read. The material is useful and informative and does submit the
material in the textbook.
Used in course