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The most often cited technological roadblock of nanoscale electronics is the "power problem," i.e. power densities and device temperatures reaching levels that will prevent their reliable operation. Technology roadmap (ITRS) requirements are expected to lead to more heat dissipation problems, especially with the transition towards...
The most often cited technological roadblock of nanoscale electronics is the "power problem," i.e. power densities and device temperatures reaching levels that will prevent their reliable operation. Technology roadmap (ITRS) requirements are expected to lead to more heat dissipation problems, especially with the transition towards geometrically confined device structures (SOI, FinFET, nanowires), and new materials with poor thermal properties.
This talk examines the physics of heat generation in silicon, and in the context of nanoscale CMOS transistors. A new Monte Carlo code (MONET) is introduced which uses analytic descriptions of both the electron bands and the phonon dispersion. Detailed heat generation statistics are computed in bulk and strained silicon, and within simple device geometries. It is shown that non-stationary transport affects heat generation near strongly peaked electric fields, and that self-heating occurs almost entirely in the drain end of short, quasi-ballistic devices. The dissipated power is spectrally distributed between the (slow) optical and (fast) acoustic phonon modes approximately by a ratio of two to one.
In addition, this work explores the limits of device design and scaling from an electrical and thermal point of view. A self-consistent electro-thermal compact model for thin-body (SOI, GOI) devices is introduced for calculating operating temperature, saturation current and intrinsic gate delay. Self-heating is sensitive to several device parameters, such as raised source/drain height and material boundary thermal resistance. An experimental method is developed for extracting via/contact thermal resistance from electrical measurements. The analysis suggests it is possible to optimize device geometry in order to simultaneously minimize operating temperature and intrinsic gate delay. Electro-thermal contact and device design are expected to become more important with continued scaling.