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Lab 1 - Introduction to Quartus II

Lab 1 - Introduction to Quartus II

This lab activity from the Digital Logic Project is designed to familiarize students with using many of the common aspects of the Quartus II software for digital logic design. Students will create a new project, create a new vhdl file, use the MegaWizard Plug-In Manager, compile the design, plan and manage I/O assignments, apply timing analysis using the TimeQuest Timing Analyzer, write Synopsys Design Contraint (SDC) files, and program a design onto the Altera DE2 Development Board.

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