Material Detail

Multi-Threaded Pipelining in a RISC Processor

Multi-Threaded Pipelining in a RISC Processor

This paper presents a model for predicting the CPI of a multi-threaded pipelined processor. It also presents the results of trace-driven simulations of single- and multi-threaded processors. These data show that, for reasonable implementation technologies, and taking into account the chip area penalty, a multi-threaded processor can achieve a lower CPI than a single-threaded processor.
Rate

Quality

  • Editor Reviews
  • User Rating
  • Comments  (2) Comments
  • Learning Exercises
  • Bookmark Collections
  • Course ePortfolios
  • Accessibility Info

More about this material

Browse...

Disciplines with similar materials as Multi-Threaded Pipelining in a RISC Processor

Comments

Log in to participate in the discussions or sign up if you are not already a MERLOT member.
  Nagel
Nagel (Student)
16 years ago
20 minutes, good content. Good look at pipelining with a RISC processor.
Learned quite a bit. A bit too detailed for someone not knowing much about
processors.
Used in course? Yes
Matt Smith
Matt Smith (Student)
16 years ago
I spent about 20 minutes reviewing the material. It is very detailed and is not
an easy read. The material is useful and informative and does submit the
material in the textbook.
Used in course? Yes
hidden