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KVD (Karnaugh Veitch) Diagrams


KVD (Karnaugh Veitch) Diagrams

Logo for KVD (Karnaugh Veitch) Diagrams
This page demonstrates KV diagrams and logic minimization. It is intended for our computer science undergraduate students. For a detailed explanation of KV (Karnaugh Veitch) diagrams see any standard computer science or electrical engineering textbook. The applets supports minimization in both disjunctive (AND-OR) and conjunctive (OR-AND) forms. Minimiziation of multiple-output functions, however, is only supported in disjunctive form. Includes tutorial and downloadable software.
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Material Type: Reference Material
Technical Format: Java Applet
CAUTION: Java Applets may not run on all browsers
Date Added to MERLOT: May 19, 2000
Date Modified in MERLOT: March 11, 2009
Submitter: John Walkup


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Primary Audience: College General Ed
Mobile Compatibility: Not specified at this time
Language: English
Cost Involved: no
Source Code Available: no
Accessibility Information Available: no
Creative Commons: unsure


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